Senior Emulation Lead
Cadence Design Systems, Inc.
SAN JOSE
hace 3 días

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Education & Experience :

  • BS or MS in EE, EECS, or CS is required
  • 8+ years relevant work experience
  • o Strong SystemVerilog skills including :

  • writing synthesizable bus functional models (BFMs)
  • o Experience writing accelerable testbenches in C or UVM-SV

    o Basic C / C++ / Embedded C is required

    o Working knowledge of build flow languages is required (eg PERL / Python / shell / Make)

    o Basic experience with any emulation system or FPGA prototyping is preferred. Both simulation acceleration and in-circuit emulation is preferred

    o Experience in PCIe is preferred. Experience in LPDDR / DDR would be helpful

    o Understanding of constrained-random, coverage-driven verification methodology using UVM-SV is preferred

    o Experience with Cadence VIP / AVIP is preferred

    o Experience of complex chip / system level debug with large environments is preferred

    o Must be an energetic self-starter, with good communication, problem solving skills and the ability to work well cross-functionally

    o Exposure to complete life cycle of silicon all the way to production is major plus

    We’re doing work that matters. Help us solve what others can’t.

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