Principal Product Engineer – Palladium Core Emulation

Cadence Design Systems, Inc.

SAN JOSE

hace 6 días

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As a condition of employment with Cadence, newly hired employees will be required to provide Cadence with proof of full vaccination, unless legally entitled to an accommodation.

Position Description :

This is a position in the Core Palladium Functional Product Enginering (FPE) team in the Hardware System Verification business unit of Cadence Design Systems Inc.

The role requires the successful candidate to execute on the launch of new products around hardware based emulation and acceleration.

Product launch requires the specification of new features, validation and characterization of the new products, and management of the rollout to Application Engineers and beta customers.

This position will involve ongoing development of test suites and regression environments, collecting and analyzing key metrics for characterizing product performance and quality.

The candidate will be expected to be able to review functional specifications and have enough HVL and HDL knowledge to create system level test suites and test plans to validate the use models.

The role will additionally demand that the candidate understands customer and field team’s requirements and can work with R&D to specify new features to meet those demands.

It will require the candidate to create material for technical training, organize field teams to help with internal testing, and will sometimes involve working with early adopters to help in the initial deployment of new features.

This role is based in Cadence’s San Jose headquarters, however the FPE team is located worldwide. As such the candidate will be expected to be self-sufficient with good communication skills, and be effective when debugging product issues and collaborating with R&D.

Position Requirements :

A BSEE with 7+ years (MSEE preferred) in the EDA / Verification industry

Excellent communication skills, both written and verbal with a proven track record of creating and delivering presentations and white papers that cover complex ideas

Strong project management and leadership skills, especially in distributed team environments

Hands-on expertise in Design Verification with a preference for experience with In-Circuit Emulation and HW Acceleration based verification

Comfortable running and debugging with verification tools such as simulators, waveform viewers, hierarchical browsers, transaction viewers at the system level

A clear logical approach to debugging complex issues with limited information

An enthusiastic and helpful demeanor, especially when supporting customers and their use of Cadence tools

Ability to travel occasionally for up to two weeks at a time for internal training or customer project support

Experience in digital design (RTL) using Verilog and synthesis tools to be able to create small synthesizable testcases

Technical expertise in functional verification using High Level Verification languages such as UVM (SystemVerilog or Specman e ) or C / C++

Familiarity with scripting in languages like Python or TCL and shell scripting

Knowledge of HW / SW verification techniques in SOC developments

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