Principal Design Verification Engineer
NXP Semiconductors
San Jose
hace 5 días

Responsibilities

  • IP and / or SOC verification with System Verilog and UVM environment
  • Very optimized small area and very low power design verification
  • Controller IP delivery and customer silicon support
  • Full ASIC design cycle from architecture, design, verification, FPGA prototyping, and silicon bring-up / validation
  • Your Profile :

  • MSEE with 5+ years of working experience
  • Bluetooth, wireless, or other networking controller design, implementation, verification experience is essential
  • Experience in SOC integration and SOC DV experience is beneficial
  • Strong with ASIC design concept and design flow : HW / SW co-simulation, UVM, synthesis(DC), Lint / CDC, and formal verification
  • Hands-on lab experience to bringing up silicon sample and FPGA pre-silicon validation is a plus
  • Fluent in System Verilog, UVM methodology, Perl, shell script, C / C++, or TCL
  • Excellent communication skills
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