PreSilicon Validation Engineer
San Jose, H, CR
hace 2 días

Job Description

Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.

Analyzes and uses results to modify testing.


Minimum Qualifications :

You should have master's degree Electrical Engineering, Computer Engineering, Computer Science, or related field or have a bachelor's degree in the above mentioned specializations with 2 years of work experience in the field.

Your experience should be in the following areas :

Background in logic design, architecture, and logic verification

Strong background in Pre-Si validation, Verilog, System Verilog and verification methodologies (OVM / UVM)

Proficiency in UNIX and Windows

Experience with programming / scripting languages like Python, Perl, C / C++

Skills pertaining to logic design and validation, including expertise in a design simulator, functional coverage concepts and implementation, testbench development, bus functional models, trackers, checkers, test development, execution, and debug

Preferred Qualifications :

Experience with 2 or more of the following :

Experience in System Verilog (OOP concepts), Testbench Components

Experience in UNIX, Scripting (Python, PERL)

Experience in building testbenches, building and incorporating validation components for stimulus generation & error reporting

Practical knowledge of SV assertions, coverage point coding

Practical and working knowledge of verification methodologies such as OVM / UVM

Experience with C++ DPI methodologies

Experience using VCS / Verdi for debug

Knowledge of Pre-Si emulation flows, working with FSDB files

Familiarity with the ASIC design flow and working knowledge of 3D Graphics

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