As a member in our Wi-Fi Connectivity Baseband design team, the candidate will be responsible for the development of our major subsystems.
Duties include but not limited to the following areas :
Block level micro-architecture design, RTL coding, verification, and documentation
Area / power optimization, and design trade-off analysis
Verification environment development and chip level verification planning and execution
Block and chip level synthesis, timing closure and formal verification
Chip bring-up and validation support
Qualifications :
MSEE with communications / DSP IC experience
Understanding ASIC design flow
Good Understanding of DSP and communications algorithms, and DSP system design specification
Experience in micro-architecture design, RTL coding, and functional verification
Proficient in design and verification tools
Good understanding of synchronous / asynchronous design, and timing requirement for complex DSP modules
Ability of power / area trade-off analysis
Experience in chip bring up and validation
Experience in system Verilog is a plus
Familiar with following common digital design tools :
Verilog design tools (Synopsys VCS, Verdi or similar)
Synthesis tools (Synopsys Design Compiler)
Lint, CDC tools (Synopsys Spyglass or similar)
Static Timing Analysis tools (Synopsys PrimeTime)
Power estimation tools (Synopsys PTPX, Spyglass, Cadence Joule or similar)
Hardware validation tool (Palladium, FPGA etc.)
Handy with common scripts (shell, Perl etc.)
Handy with laboratory debug tools on chip support (Logic Analyzer, Oscilloscope)
NXPis an Equal Opportunity / Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and / or expression, marital status, status as a disabled veteran and / or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.
In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
