Senior Principal Software Engineer - FPGA Prototyping Platform Compiler Team (R34190/as)
Cadence Design Systems, Inc.
hace 6 días

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. With Cadence® Protium™ prototyping platforms, design and verification teams can rapidly bring up a prototype and provide a pre-silicon platform for early software development, system validation, and hardware regressions.

As part of the Compiler team you would be responsible in adding compelling feature and improving performance of the Protium Prototyping Platform.

The Sr. Principal Software Engineer will be responsible in design and development of new features and algorithms to improve the Protium Platform.

The Principal Software Engineer will accomplish this by interacting with team spread across different geographies. The candidate is also expected work with technical support lead and key customers to resolve implementation or usage issues.

You will be a key member of an R&D team in the field of EDA algorithmic software development for FPGAs. You will be working with a dream team on providing a breakthrough solution in the multi FPGA prototyping space.

The ideal candidate will have the following skills and experience :

  • BS / MS / PhD in CS or similar
  • A minimum of at least 6 years of relevant industry experience in algorithmic software development for FPGAs
  • Strong desire and ability to work in a fast-paced startup environment
  • Eagerness to learn and master new technologies and build the best systems possible.
  • Very strong development experience in a general-purpose language (e.g. C++, C#, Java)
  • Strong CS fundamentals background in data structures, algorithms, systems architecture
  • Experience in logic optimization, compilation of RTL memory models, Arithmetic Operators, optimizing the mapped elements based on area / delay tradeoffs.
  • Ability and desire to work on all parts of the stack (algorithms, databases, UI) and revisit traditional synthesis and optimization algorithms using emerging technologies in machine learning and big data.
  • Knowledge of Logic Simulators and exposure to multi-threaded / concurrent programming are pluses.
  • An incredible desire for quality and perfection... and the judgement to temper it when necessary to ship.
  • A healthy sense of fun!
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