At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
Looking for highly accomplished engineering leader to join a team of highly skilled developers working on state-of-the-art timing closure system.
Job duties will include working with a high performance team of engineers on timing analysis and closure methods, addressing the most challenging designs in the industry for optimizing power, performance and area at advanced technology nodes.
Responsibilities will require significant innovation to advance the state-of-the-art algorithms for timing closure, and software implementation in C++ with multi-threading and distributed processing,
Candidate must have an MS or Ph.D. in EE or CS, with minimum 15 years EDA software development experience in static timing analysis and optimization, physical design optimization, using C++ with emphasis on multi-threaded and distributed processing.
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