The candidate would be responsible for :
Conception and implementation of chip-level mixed signal simulation environments (testbenches, run scripts, etc...).
Develop self-checking simulations and models.
Establish the AMS Verification Plan
Coordinate the verification tasks and respect schedules and deadlines
Progress reporting and communication with Tier 1 customers
Profile :
MS or PhD in Electrical Engineering
The candidate should have at least 5 years of experience in AMS verification.
Must be knowledgeable in both analog and digital design fundamentals.
Must have good debug analysis skills.
Good communication skills (written and verbal)
Proactive and detail-oriented
Expertise in following tools and standards :
Cadence AMS designer (both ADE-XL / Maestro and command-line)
Hierarchy Editor configuration and verilog configurations
Custom connect modules and connect rules and / or IE cards
Spice / Spectre / APS / XPS simulator : able to solve slowness, convergence issues.
Real-Number Modeling : wreal, SV, User-defined Types / Nets (EE package)
Would be a plus :
Systemverilog Assertions
UVM-MS concepts. Ideally able to setup a UVM-MS environment
Some knowledge of C / DPI / VPI
NXPis an Equal Opportunity / Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and / or expression, marital status, status as a disabled veteran and / or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.
In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
