Principal Design Engineer DDR
Cadence Design Systems, Inc.
SAN JOSE
hace 5 días

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As a Principal Design Engineer you will be responsible for post silicon Validation, testing and characterization. Additionally, you will own an in-depth silicon bring-up, functional validation and PVT characterization of DDR IP and Memory sub-system interface.

Responsibilities will include, but are not limited to the following :

  • Collect structured test measurement data and perform data analysis
  • Develop and execute comprehensive test plan using high-end equipment (scopes, BERTs)
  • Participate in validation and characterization of critical sub-blocks like high-speed IOs, DDR Power management system etc.
  • Develop and optimize comprehensive test automation
  • Participate in collateral development (characterization reports)
  • Work closely with other DDR teams to understand chip architecture, hierarchy and provide feedback on silicon performance, margin to designed specification for helping improve and fine tune IP design
  • Qualification and Required Skills :

  • M.S. or BSC Electrical / Computer Engineering (or similar degree)
  • A minimum of 5 years of relative experience
  • Strong debug and problem-solving skills
  • Prior experience with Silicon validation and characterization of DDR subsystems
  • Prior hands-on experience with high-end lab equipment such as Scopes, BERTs, AWGs, temperature controllers, programmable power supplies
  • Prior experience with test automation program development (using C / C++)
  • Prior experience with PCB design, debug and signal integrity will be helpful
  • Good understanding of electrical signaling aspects
  • Ability to clearly communicate technical challenges.
  • Experience with DDR memories desirable
  • Knowledge of SOC platforms
  • Strong communications skills
  • We’re doing work that matters. Help us solve what others can’t.

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