At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are seeking an experienced signal integrity / power integrity engineer to support package and PCB for the DDR test chip, to analyze the signal integrity and power integrity of DDR system, to provide development guidelines and customer support for the latest DDR / HBM interface.
The position combines the role of the signal integrity and design engineer, provides a unique opportunity to work on next generation DDR interface, and steer industry standards.
Support the package / PCB of the test chip for the high-speed DDR / HBM interface
Channel model and PDN model generation, signal integrity and power integrity simulation.
Develop flow and methodology for the DDR signal integrity and power integrity analysis.
Develop DDR package and PCB guidelines for the internal and external customers.
Provide the feedback to IP developers regarding DDR roadmap, architecture, topology, and design improvements.
Support the customer engagements including guidance on board and system design.
minimum 2-3 years of experience
Familiar with package and PCB design process
Good experience in modeling of signal and power delivery channels (package, PCB, interposer, HBM)
Good experience in the frequency domain and time domain analysis of Power Distribution Networks.
Good experience in the high-speed DDR channel analysis.
Good oral and written communication skills
Team player, willing to take on a variety of projects
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