At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Cadence DDR team is looking for an experienced, hands-on Verification leader who will lead projects to design and implement multiple verification testbenches.
IP products cover the range of controllers and PHY across DDR, LPDDR, HBM, GDDR6 protocols. This is a technical leadership position setting the vision and technology direction for an experienced worldwide verification team dealing with multiple products.
Qualifications and Skills include, but are not limited to the following :
Experience in architecting modern coverage driven verification testbenches and deploying them on successful products
Deep understanding and knowledge of verification methodologies flow and quality metrics covering Simulation, Formal, Emulation, FPGA
Hands on and In-depth knowledge of UVM methodology, System Verilog, Coverage and scripting languages
Highly experienced with defining block, sub-system, and SOC top-level test plans.
Prior experience in dealing with dynamic and configurable testbenches highly preferred
Capability to provide mentorship to engineers to improve Design Verification quality
Great debugging and problem-solving skills.
Great interpersonal communication skills.
Protocol knowledge like DDR, AXI / AMBA, CHI is preferred.
Prior people management experience is a plus
At least 10 years of proven experience in SoC / ASIC verification.
Bachelor or Master's Degree in electrical engineering, computer science or related degree
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