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Physical Design Engineer, SoC / NOC

We are looking for a talented individual to work in the DEG (Design Enablement Group) team of the Cadence Tensilica IP. Tensilica has unique technology to build configurable and extensible processor IP as well as system level design such as SoC (System on Chip) an NoC (Network on Chip).

In this team, among other things, we develop methodology and implementation flows that can achieve the best possible PPA (Power, Performance and Area) for these processor IP and the overall system.

Roles and Responsibilities :

Minimum Requirements :

1. MS / Ph.D. in EE / CS

2. Ph.D. and 5+ or MS and 7+ years of physical design working experience on advanced nodes

3. Strong understanding of digital logic design, processor design, computer architecture

4. Strong knowledge of SoC subsystem including processors, NoC fabric, memory subsystem design and architecture

5. Must have excellent knowledge of ASIC design flows and issues

6. Good working knowledge of Perl, or any other scripting language, is required

7. Strong verbal and oral communication skill

8. Must be an excellent team player in a fast-paced environment

Preferred Requirements :

1. Prior experience on any Cadence physical implementation tool

2. Working on power analysis and optimization methodology

3. Programming skills in C / C++ and be able to read code in Assembly

4. Hands on working experience of automation with Perl / Python, Makfile, Shell scripting

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