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Intel
San Jose, H, CR
hace 10 horas

Job Description

Come and join our task force, you will be responsible for design methodologies and CAD support of digital blocks from complex AMS IPs like HSIO, DDR- Ethernets- PLL, etc.

Key responsibilities include but are not limited to

  • Physical Design logic signoff in STA and Low Power on advanced process nodes 10nm and below.
  • Work closely with Design teams to understand the design and convergence challenges plus derive methods to provide recipes with a focus on PPA and Turnaround time optimizations.
  • Work with internal IP design implementation teams on tactical implementation and design closure aspects and enable design teams in all aspects of Physical Design OR Timing Signoff wrt Tools Flows and Methods.
  • Understand project schedules and foresee design team requirements. Extensive communication required with customers in multi-geographic regions.
  • Work with 3rd party EDA vendors and internal IP teams to resolve issues and drive improvements in vendor tools design convergence and signoff.
  • QUALIFICATIONS :

  • Studies completed in the fields of computer engineering science and with prior experience with strong focus in Methodology development, flow automation and support in Physical design construction and signoff domains.
  • Knowledge with the following circuit design areas : Timing, Noise analysis, Low power
  • Experience in 1 or more of the following : ASIC Physical Design RTL to GDSII Implementation flow in areas of floor planning, power planning, placement, CTS routing or in areas of Timing analysis, timing convergence, SINoise analysis, Signoff quality, PVT derate analysis, design guard banding, Timing lib generation, Physical View Generation, LEF NDM etc.
  • Team player with good problem solving and communication skills in English and Spanish
  • Automation skills in PERL and or TCL and or Python
  • Desired :

  • Any STA closure convergence execution with Low power design closure is a plus
  • ICC2, FusionCompiler, Innovus, PrimeTime, Tempus, Conformal, VCLP EDA tool knowledge at advance user level will be considered a valuable plus
  • Web development DB SQL and Power BI knowledge are added pluses
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