At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence has an opportunity for a self-driven and highly motivated software engineer to join our research and development team in San Jose to work on our cutting-edge emulator’s logic synthesis and front-end tool development. The duties include :
New VHDL, Verilog, and System Verilog language feature development.
Logic optimization and performance improvement
Emulation specific front-end and synthesis development
Position Requirements :
Solid C or C++ programming capability
Experience with VHDL, Verilog and System Verilog
Bachelors in Computer Science, Electrical or Computer Engineering + 4 years of related experience
Masters in Computer Science, Electrical or Computer Engineering + 3 years of related experience
Ph.D. in Computer Science, Electrical or Computer Engineering with no experience
We’re doing work that matters. Help us solve what others can’t.