At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This individual is the primary focal point for technical issues, questions, and discussions for a given project. Leads technical discussions with customers and is the primary technical interface with the Cadence PM.
Capable of influencing outcomes among customers, R&D and Cadence technical team members.
We need a pro-active, enthusiastic, customer-facing solution engineer who is an expert in circuits, design and timing analysis.
This person will be focused on working with customer in Signoff solution space.
The ideal candidate should have :
1) Understands ASIC Design implementation process and steps
2) Strong hands-on experience with Synthesis (Genus, RTL Compiler, Design Compiler)
3) Exposure and experience with Test products (Modus, Encounter Test, Logic Vision, DFT Compiler etc)
4) Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)
5) Strong STA and SDC debugging abilities are required.
6) Low power analysis, Clock design / analysi and hands-on 16 / 14nm experience a plus.
7) Ability to understand and write RTL (System Verilog, Verilog, VHDL)
1) Requires a BS or MS in EE with 10+ years industry related experience in design and EDA (Digital Implementation / Signoff)
2) Experience using Digital software with at least one major EDA vendor flow. Automation skills using Perl, Tcl and shell scripting essential
3) Strong analytical & analysis skills covering digital implementation is critical.
4) Proven track record and experience working in a fast paced environment
5) Excellent customer interaction & presentation skills
Should have exposure in :
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