At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Looking for accomplished software engineer to join a team of highly skilled developers working on state-of-the-art timing closure system.
Job duties will include working on very high capacity data-model to represent full-chip physical data, a high performance GUI for representing and editing hierarchical full-chip data, and optimization methods for automatic and semi-automatic timing closure.
Candidate must have MS or Ph.D. in EE or CS, with minimum 5 years EDA software development experience in data-model, GUI, static timing analysis and optimization or related areas, using C++ and tcl.
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