At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Our team is looking for a candidate with a strong background on Synthesis, LEC, CLP, Constraints, P&R and timing analysis fundamentals
Understands IC design with exposure to 13nm & below process nodes
Experience with EDA tools in the IC digital implementation & signoff flows
Low power analysis and hands-on 7 / 5nm experience a plus.
Strong Tcl / Perl programming background is a must.
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