Digital Front End Implementation Engineer
Intellipro Group
San Jose
hace 3 días

Overall Responsibilities :

  • Lead the effort on synthesis and optimize IP core for timing, area and power (PPA)-Work with backend team on floorplan and P&R-Work with SOC team on clock, reset, timing and power related tasks-Develop, maintain, and improve existing flows for Synthesis, Formal and STA.
  • Support multiple Ips-Work with SOC implementation engineers to integrate your solutions in SOC flows. Mandatory Skills : -3+ years of experience in relevant field-Basic understanding of digital design and VLSI concepts is required-Fluent with HDL languages (Verilog, SystemVerilog)-Experience in Synthesis tools Design Compiler is required-Experience in STA tools Prime Time is required-Experience in UPF low power flow is required-Experience with Formal equivalence tools such as Conformal LEC and / or Formality is required.
  • Experience scripting in TCL, Perl, or Python is required-Must have strong communication skills-Attention to detail and desire to learn.
  • Experience with large scale digital design at high frequency (>
  • 1GHz) preferred-Experience in Physical Synthesis preferred

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