At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is an opportunity to contribute and innovate in the design of next-generation Memory subsystem Design IPs at Cadence.
These advanced technology node IPs will enable the futuristic SoCs for Datacenter, Edge computing, Automotive and AI applications.
As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes developing micro-architecture / design specifications, implementing RTL code for complex digital logics, RTL integration, synthesizing and optimizing the design for better timing, PPA, doing performance analysis, setting up block level test bench, collaborating with the Analog and verification team and analyzing the coverage results.
You will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R, and participating in silicon bring up with the validation team.
You will be working and interacting with accomplished digital and analog circuit designers. You will work in a dynamic, team environment and must be an effective team player on projects.
You will have ample opportunities to expand your knowledge, expertise and skillset. You would also be contributing to futuristic clocking architecture, design micro-architecture and RTL design decisions targeted at better timing, PPA, based on pre and post implementation timing analysis.
This is an opportunity to work and interact with accomplished digital and analog circuit designers and timing experts who has built industry leading multi protocol memory PHYs for over a decade.
Required Experience & Qualifications
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