In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be working on signoff design methodologies of complex and world class Graphics IPs.
In this position, your responsibilities will include, but not be limited to :
Developing timing flows, understand design requirements / objectives and develop signoff conditions and milestone checklists appropriate with the design project goals.
Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff
Required Qualifications :
You should have master's degree Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years' experience or have a bachelor's degree in the mentioned specializations with 3+ years of work experience, both with focus in Methodology development and flow automation in Timing & Low-Power Signoff
Intermediate to Advanced English Level
Experience and / or knowledge in ASIC Physical Design RTL to GDSII flow in areas of timing analysis, timing convergence, SI / Noise analysis, signoff quality (PVT, derate analysis, design guard banding, etc), Timing ECOs, PV / Noise modelling, .libs, etc.
EDA tool knowledge : Primetime / Tempus, STAR-RC, ICC2 / FusionCompiler / Innovus / Genus
Automation / scripting skills in Tcl and Perl / Shell / Python coding for robust flow implementation is a required expectation.
Any STA closure / convergence execution with low power design closure is an added advantage
Team player, with good problem solving and communication skills
Preferred : 6+ years' experience
6+ years' experience