STA/Signoff methodology implementation engineer
San Jose, H, CR
hace 1 día

Job Description

In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be working on signoff design methodologies of complex and world class Graphics IPs.

In this position, your responsibilities will include, but not be limited to :

  • Defining and implementing signoff methodology for all areas related to Performance Verification (PV) including timing analysis, power estimation, Circuit Quality, Extraction and noise glitch analysis across internal and external foundry processes
  • Developing robust ASIC design and verification methodology to meet PV requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints / exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure
  • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV / Si miscorrelation effects in timing analysis flows
  • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations
  • Developing timing flows, understand design requirements / objectives and develop signoff conditions and milestone checklists appropriate with the design project goals.

    Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff


    Required Qualifications :

    You should have master's degree Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years' experience or have a bachelor's degree in the mentioned specializations with 3+ years of work experience, both with focus in Methodology development and flow automation in Timing & Low-Power Signoff

    Intermediate to Advanced English Level

    Experience and / or knowledge in ASIC Physical Design RTL to GDSII flow in areas of timing analysis, timing convergence, SI / Noise analysis, signoff quality (PVT, derate analysis, design guard banding, etc), Timing ECOs, PV / Noise modelling, .libs, etc.

    EDA tool knowledge : Primetime / Tempus, STAR-RC, ICC2 / FusionCompiler / Innovus / Genus

    Automation / scripting skills in Tcl and Perl / Shell / Python coding for robust flow implementation is a required expectation.

    Any STA closure / convergence execution with low power design closure is an added advantage

    Team player, with good problem solving and communication skills

    Preferred : 6+ years' experience

    6+ years' experience

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