At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is an opportunity to contribute and innovate in the design of next-generation Memory subsystem Design IPs at Cadence.
These advanced technology node IPs will enable the futuristic SoCs for Datacenter, Edge computing, Automotive and AI applications.
As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow and primarily, IP and block level synthesis and timing closure ownership throughout the entire project cycle.
You would be responsible for generation of block and full chip timing constraints, development and maintaining sign-off methodology and flows related to timing verification and closure across advanced technology nodes.
You would also be contributing to futuristic clocking architecture, design micro-architecture and RTL design decisions targeted at better timing, PPA, based on pre and post implementation timing analysis.
You will be closely interfacing with the internal Physical Design team on STA, timing closure and P&R, and also provide guidance on SoC level timing closure to customers using Cadence IP.
This is an opportunity to work and interact with accomplished digital and analog circuit designers and timing experts who has built industry leading multi protocol memory PHYs for over a decade.
You will work in a dynamic, team environment and must be an effective team player on projects. You will have ample opportunities to expand your knowledge, expertise and skillset.
You may interact with marketing, support, verification, sales, and customers.
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