At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Join us to architect and develop the leading edge debugging and analysis tools for today's complex SoCs. Members of our team develop products to enable software driven development, debug and validation using Cadence virtual simulators, RTL simulators, hardware emulators and FPGA prototyping systems.
Develop innovative approaches to integrating these execution engines with each other to enable debug use models.
Key Qualifications :
Bachelor's or Master's Degree or higher with minimum 15 years industry experience
Deep knowledge of event-based HDL simulation and / or emulation / prototyping engines and integrating such engines together
Deep hands-on development experience in HDL simulators, emulation software a must
Experience with synchronization and coordination across multiple HDL run time engines is very desirable.
Experience developing control and synchronization protocols to enable debug interfaces is a big plus
Good knowledge of customer use models for large SOC validation
Additional skills that are important :
Experience leading multi-person projects and excellent collaboration abilities
Strong hands-on software engineering and development skills using C++ and C
Demonstrated ability to drive novel solutions to complex problems
Strong English verbal and written communications skills
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