Engineer - Digital SoC Synthesis, STA, Timing Constrants, FV and ECO (San Diego OR Bay Area)
San Jose
hace 4 días

Job Overview : Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.

But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products.

This is the Invention Age - and this is where you come in. The QCT GSoC team is looking for bright engineers with excellent analytical and technical skills.

This is a golden opportunity to be part of a fast-paced team responsible for delivering the design / flows for high performance & high quality SoC silicon on the latest process nodes at 7nm and beyond.

  • We are seeking candidates with at least 1-2 years industry experience in the area of logic synthesis, timing constraints, formal verification and / or functional ECO.
  • New grads and candidates with under 1 year experience will not be a fit for this role.* Ideal candidates will possess top level SoC implementation, bridging the RTL and physical design worlds, including physical synthesis, formal verification, timing constraint creation / validation and functional ECO creation.

    Minimum Qualifications - Bachelor's degree in Science, Engineering, or related field. - 5+ years ASIC design, verification, or related work experience.

    Preferred Qualifications - 5+ years experience in logic synthesis, formal verification, timing constraint creation / validation and / or functional ECO creation.

  • Perl / tcl / python expertise
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