At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) and experience are required.
Design experience should include ASIC design using industry-standard hardware description languages (Verilog / SystemVerilog)
Demonstrated skills at understanding customer needs and identifying solutions to their challenges with Cadence digital design tools
Exposure to digital IC design and experience in applying solutions in the RTL-GDSII digital space
Demonstrated ability in customer tool debug and usage issues (on-site and remote)
Close collaboration with R&D on issues using established protocols
Communicate with customers on issue workarounds and new tool fixes
Participate in customer benchmark activities and pre-release code bashing with DSG products
The candidate must have demonstrated experience in several of the following areas :
Design constraint creation (SDC) & debug
Static timing analysis, Power Analysis (Static, Dynamic, Leakage)
Timing optimization, in logical and physical mode
Low power implementation with knowledge of UPF
Must have excellent debugging skills and an ability to separate out the critical issues from trivial ones.
Scripting experience with moderate / advanced TCL scripting skills is a must have
Outstanding oral communication skills to deliver customer and marketing presentations, product updates, etc.
CAD flow develop / debug / optimize
The candidate will have broad knowledge experience in the physical design process of modern SOCs (16 / 7nm or below).
The candidate will possess a self-starter mindset with an established track record of complex problem solving in SOC physical design.
The candidate should possess excellent communication skills and be adept at working with both customer engineers / mgmt.
as well as Cadence team members
MS or BS Computer / Electrical Engineering with 5-10 years experience
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