Sr. Static Timing Analysis Engineer (STA)
San Jose
hace 5 días

Company :

Qualcomm Atheros, Inc.

Job Area :

Engineering Group, Engineering Group >

General Summary

Digital - Oversees definition, design, verification, and documentation for ASIC development for a variety of products. Determines architecture design, logic design, and system simulation.

Defines module interfaces / formats for simulation. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.

Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as National Instrument (NI) products, LabVIEW, and MathWorks MATLAB, SIMULINK, VISIO and other toolboxes.

Uses language such as HDL, C, PERL. Provides technical expertise for next generation initiatives.

Responsibilities :

  • STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
  • Timing analysis, validation and debug across multiple PVT conditions using PT / Tempus.
  • Run Primetime and / or Tempus for STA flow optimization and Spice to STA correlation.
  • Evaluate multiple timing methodologies / tools on different designs and technology nodes.
  • Work on automation scripts within STA / PD tools for methodology development.
  • Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
  • Experience in design automation using TCL / Perl / Python.
  • Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT / Tempus
  • Familiar with process technology enablement : Circuit simulations using Hspice / FineSim, Monte Carlo.
  • Familiar with CLP and low power design methodology and be able to debug the low power design issues.
  • Preferred Qualification / Skills

  • Strong expertise in STA timing analysis basics, AOCV / POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
  • Hands-on experience with STA tools - Prime-time, Tempus
  • Hands-on experience with CLP tools.
  • Knowledge on PD tools and flow is a plus.
  • Have experience in driving timing convergence at Chip-level and Hard-Macro level
  • In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
  • Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
  • Knowledge of Spice simulation Hspice / FineSim, Monte Carlo. Silicon to spice model correlation.
  • Proficient is scripting languages TCL, Perl, Awk
  • Basic knowledge of device physics
  • Physical Requirements

  • Frequently transports between offices, buildings, and campuses up to ½ mile.
  • Frequently transports and installs equipment up to 5 lbs.
  • Performs required tasks at various heights (e.g., standing or sitting).
  • Monitors and utilizes computers and test equipment for more than 6 hours a day.
  • Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.
  • Minimum Qualifications

    Education :

    Bachelors - Engineering, Bachelors - Science

    Work Experiences :

    2+ years ASIC design, verification, or related work experience.

    Certifications : Skills :

    Skills :

    Preferred Qualifications

    Education :

    Bachelors - Computer Engineering, Bachelors - Computer Science, Bachelors - Electrical Engineering

    Work Experiences :

    2+ years experience with scripting tools and programming languages. ,2+ years experience with architecture and design tools.

    4+ years ASIC design, verification, or related work experience. ,2+ years experience with design verification methods.

    Certifications : Skills :

    Skills :

    ASIC Verification, Matlab C, Multicore System-On-Chip (SoC), Perl Programming, Simulation Software

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