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Principal Design Engineer Tensilica IP Backend Physical Design

The Cadence Tensilica Processor Core is used in high performance blocks of complex SoC's. This is one of the best-kept secrets within the semi IP world, powering AR / VR, HiFi Audio and Speech, Vision, Imaging and hundreds of intelligent IoT applications.

The Tensilica processor family contains the next generation of embedded cores that meet the demands of AI / ML edge computing.

We are extending the reach of our platform to help companies like Amazon, Facebook, Google, Microsoft and Intel embed our core into their product portfolios.

Come be part of the next explosion of embedded devices building a key part of our processor generating platform for CPU's and DSP's.

Position Description :

Searching for an intelligent, inventive, self-starting engineer interested in developing new backend flow methodologies with the Cadence EDA toolset.

You will be joining a small team of capable individuals with significant visibility throughout the entire Tensilica IP group within Cadence.

You have a strong understanding of all stages of placement, CTS, routing, extraction and timing signoff, with a goal of optimizing power / performance / area of complex multi-processor Tensilica subsystems.

Experience with the latest process technologies and concepts (CNOD leakage, via pillars, layer promotion, etc.) a plus.

Responsibilities :

40M gate) multicore solutions

Requirements :

High value additional skills :

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