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The Physical Verification R&D Solutions Software Engineering (LVS / PERC focus) role is a multi-faceted position encapsulating a mix of expert-level physical verification methodology development, software performance / accuracy analysis, and optimization programming (Python, C++).
R&D Solutions engineers bridge software architecture development and end-user software deployment by designing, prototyping, and profiling methodologies to enable next-generation physical verification solutions with superior performance and usability.
R&D Solutions engineers also provide methodology and flow guidance to engine developers across multiple physical verification subdomains, to ensure that code development satisfies the requirements for successful semiconductor design flow deployment.
This R&D Solutions role is focused on flow development, analysis, and optimization in the Layout-Versus-Schematic (LVS) and Programmable Electrical Rule Check (PERC) physical verification subdomains.
This role also requires a sound working knowledge of how LVS and PERC are exercised by layout designers, to validate successful schematic correspondence and tolerance of adverse on-chip electrical phenomena (e.
g., ESD events). The engineer will employ expertise in LVS / PERC rule file commands and software algorithms, in order to design, validate, and optimize behavioral and reporting solutions within the Cadence physical verification product that are both performance-efficient and intuitive to the layout designer.
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