Design Architect
hace 4 días

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Summary

Cadence Design Systems is looking for a PHY Architect to participate in the PHY Architecture development for modular, scalable, high-performance, low-power, next-generation Memory Interfaces on latest process technologies.


  • Defines, Documents and Designs PHY Architectures for High-Performance / Low-Power Memory Interfaces supporting multiple SOC applications.
  • Architecture study of DDR, GDDR, LPDDR and HBM memory subsystems.
  • Work with a team to define PHY RTL & timing constraints and provides guidance to Design verification and Physical design.
  • System Modeling, Architecture, Design and Development of high performance, low power IO PHY meeting latest Memory Industry Standards for LPDDR, DDR Or Proprietary On-Package Interconnects standards.
  • Collaborate across functional teams - Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best In Class Power, Performance and Area metrics.
  • Collaborate with SoC integration teams on PHY level requirement and integration issues.
  • Mentor and develop technical leadership pipeline.
  • Requirements

  • Experience in PHY Architecture, Circuit / Logic Micro-Architecture definition of High Speed Memory Interfaces example DDR, LPDDR, GDDR, or On-Package Interconnect IO interfaces, Ultra Low Power Die-to-Die IO.
  • Design achieved production in high volume and extensive exposure on post-silicon debug and Hardware and Firmware based PHY training algorithms

  • Hands-On Experience in high speed design building blocks for High Speed Interfaces, RTL logic design, Synthesis, Physical design, Power analysis and / or integration aspects for IO PHY in SoC
  • Understanding of LPDDR / DDR / GDDR JEDEC specifications and related Memory Interface Protocols
  • Knowledge of DFI based Memory Sub-systems, Power / Performance optimization and Package / Platform trade-offs is required.
  • PHY Architecture knowledge needs to span multiple domains (Analog, Digital, Platform Electricals, etc.)
  • Understanding of design for yield and exposure to production challenges in latest technology process nodes.
  • Cross-discipline knowledge in any of these areas, such as Analog integration, RTL / System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training and Architecture specification documentation.
  • Strong written, oral communication and presentation skills
  • Bachelor of Science degree with at least 15+ years additional experience, or a Master of Science degree with at least 10+ years additional experience, in Computer Science, Computer Engineering, or Electrical Engineering.
  • About the Company

    Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation industry.

    This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs, System-On-Chip devices, IP and complete systems at lower costs and with higher quality.

    Cadence® Denali® Memory and Storage IP solutions support the widest range of industry standards, with controller and PHY implementations for both high-performance and low-power applications.

    Take advantage of widely used memory and storage protocols including the latest DDR, LPDDR, NAND Flash, Octal SPI, Quad SPI, and SD / SDIO / eMMC standards and get the added value of configurability and customization support for your specific needs.

    Robust Hard PHYs are backed by complete characterization reports for high-performance apps, while Firm PHY options provide flexibility.

    Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

    We’re doing work that matters. Help us solve what others can’t.

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