At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job opening is for a R&D CPU Design Architect roles with primary emphasis on CPU architecture and RTL design. The role of CPU design architect requires 10+ years of industry experience in CPU RTL design.
The CPU team in Cadence is focused on architecture, simulation, design, design verification, physical design as well as building software and firmware development toolchains and is building a CPU roadmap covering both embedded CPUs from low power to high performance superscalar architectures, as well as application CPUs capable of running Linux and Android.
We are looking for an experienced RTL design engineer to be a part of our worldwide CPU R&D team within Cadence. If you are a passionate and dynamic individual, with at least 10 years of industry experience in processor RTL design, and with domain expertise in design and RTL implementation of CPU subsystems such as processor caches, branch predictor, load / store pipeline, execution units or vector processing units, and if you are interested in working on next generation designs - we are interested in talking to you.
You would be a part of a global R&D team, working alongside some of the highly skilled CPU design, verification and software architects in Cadence, and enriching your own experience on latest challenges in IoT, embedded systems and datacenter compute solutions.
The ideal candidate should have BS or MS degree in EE or CS or related degrees and 10 or more years of industry experience in RTL design for CPUs or DSPs, and following qualifications : 1.
RTL implementation level understanding of CPUs 2. Hands-on experience with designing of several CPU subsystems, such as CPU caches, branch predictors, execution units, Load / store pipeline and last level cache controllers 3.
Understanding CPU design verification flow and UVM based Design verification flows where embedded CPUs are used and coordinating with verification teams 4.
Familiarity with interconnect and debug interfaces such as AXI, ACE, CHI, APB etc. 5. Strong written and verbal communication skills 6.
capability to work in international and diverse environments.
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