At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is an opportunity to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols.
The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows.
The candidate will primarily be responsible for front-end coding, scripting and developing flows at all phases of the digital design and functional verification.
It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with the digital, analog and application teams.
Candidate should be willing to work full time in the San Jose office.
The ideal candidate will have a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status.
This includes but is not limited to :
Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly preferred.
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