GEO Semiconductor Inc
San Jose
hace 4 días

About GEO Semiconductor

GEO Semiconductor (GEO), headquartered in San Jose, CA, is an industry leader in delivering programmable camera video processors to the rapidly growing automotive camera market.

GEO’s products feature advanced image signal processing, unique eWARP® processing technology, and state of the art neural network-based computer vision solutions.

GEO ships camera video processors in diverse automotive applications such as ADAS, autonomy, in-cabin monitoring, digital mirrors, smart backup and augmented reality cameras.


GEO is looking for an ASIC Design Engineer that brings not only exceptional RTL design skills but also a history with embedded Root of Trust / Hardware Security Module experience.

Located in the San Jose or Toronto office, you will have the following responsibilities :

  • Configure & integrate RISC-V oriented Hardware Security Module IP that will address automotive secure boot, key storage & crypto acceleration
  • Specify & document the overall Security architecture for the SoC
  • Define & document the top-level architecture for authentication of system elements (sensors & downstream SoCs)
  • Define & document the top-level architecture for video payload authentication & encryption
  • Sort out build vs buy decision on video payload crypto acceleration module
  • Own the MIPI Security aspect of the product roadmap as the standard is released & as it evolves
  • Develop block / system level RTL to meet synthesis / physical, DFT and power goals
  • Develop block architecture & RTL that will meet the Functional Safety (FuSa) requirements of the chip
  • Collaborate with the physical design team to meet overall physical design targets
  • Work with the verification team to develop & review test plans for your blocks
  • Work with the systems and software teams on emulation platforms and lead the bring-up of your blocks

  • BSEE
  • 5 years of industry experience in digital design
  • Prior experience with Root of Trust / Hardware Security Module implementations
  • Experience in RTL design with Verilog / System Verilog
  • Understanding of standard IC design methodology with simulation, synthesis, timing closure and DFT
  • Ability to work collaboratively with a verification team
  • As a GEO team member, you have a passion to solve complex technical challenges and define ground breaking innovations in camera processing.

    You are highly motivated and hands-on with excellent interpersonal skills.

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