The Foundational Security team (FST) is looking for digital logic designers and validators keen to work on a scalable IP design.

Candidate will be responsible for design and validation of new IP roadmap features as part of FST’s HW IP developing HW security for various market segments across Intel.

As a member of the team, the candidate would be responsible for driving scalable IP development while also making the Design Integration and SOC delivery a fully automated solution.

Candidate will be part of an IP team working closely with other verification engineers, RTL design engineers, micro-architects, and other team members in determining the proper implementation strategy for new design, ensure quality of design, and develop test-plans, verification environment, and drive delivery to SoC.

They will have an opportunity to learn and contribute towards making Intel Hardware more secure!

Behavioral traits :

Qualifications

Minimum Qualifications :

The candidate must possess a minimum of bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.

2+ years of relevant logic design / pre-silicon verification experience with multiple project cycles.

2+ years of logic design / pre-silicon verification experience with various tools and methodologies including but not limited to :

Capable in developing testplans, tests and verification environment based on High Level Architecture specifications.

Work experience with system Verilog or OVM or UVM or Object-Oriented Programming (OOP)

VLSI or Structural and Physical design flow / methodology experience.

Power management, IOSF, AHB, PCI express or any industry standard BUS protocol experience a plus.