Structural design RLS flow automation engineering student and library collateral delivery
Intel Corporation
San Jose, CR
hace 2 días

Job Description

If you are studying to get an engineering major or master's degree in Electric-Electronic Engineering, computer sciences or embedded systems, you have a curious mind that enjoys to deep dive and implement solutions, you are eager to learn and work in top of the notch technology and you are within 1 year of getting your university degree (plus or minus 6 months), then we are looking for you.

As a student contributing in leading-edge RLS team you will have the opportunity to balance your classes while learning in many of the available focus areas within this team.

RLS team offers you technical career growth opportunities such as : working with industry leading foundry technologies, working with EDA vendors on development of next generation capabilities, breakthrough innovation in low power optimizations, inclusive work environments, access to principal engineers and highly competitive team members from which to learn from and codevelop methodologies and solutions that will directly impact Intel's GPU product roadmap.

In this team, you can grow and contribute in many different internal sub-scopes such as : ML / AI applied techniques, improve synthesis placement and routing to foster a better design convergence, clock tree implementation, power efficiency, library collateral delivery, floor planning, interface with DFX architects to implement SCAN flows to guarantee high coverage, timely design convergence and reliable chain connectivity algorithms to detect issues.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Experience listed below would be obtained through a combination of your school work / classes / research and / or relevant previous job and / or internship experiences.

Minimum Qualifications :

  • Studying Bachelor's Degree, "Licenciatura" or Master's Degree in Electronic, Electrical engineering, VLSI, Computer Science
  • 6 months of academic experience in topics such as : VLSI, Synthesis place and route tools, structural design flow automation, digital design, DRC convergence (School or previous assignment are ok)
  • Fluent written and spoken English (Advanced Level)
  • Immediate availability
  • Experience scripting languages : Python and TCL.
  • 1 year internship
  • Preferred Qualifications :

  • Experience with Synopsys suite basics : ICC, Design Compiler, Fusion Compiler, Library compiler
  • Interpret Verilog or System Verilog netlists and older scripted languages such as PERL
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