Principal Physical Design Engineer
Cadence Design Systems, Inc.
SAN JOSE
hace 5 días

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As a condition of employment with Cadence, newly hired employees will be required to provide Cadence with proof of full vaccination, unless legally entitled to an accommodation.

Principal Physical Design Engineer

Location San Jose, CA preferred (remote possible)

You will work with an elite team of physical design implementation engineers and have personal design responsibility, including floor planning, power grid, place and route, advanced clock tree synthesis, timing closure, power / signal integrity signoff, physical verification (DRC / LVS / Antenna), EM / IR signoff, DFM Closure.

You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed DDR / GDDR PHY designs in advanced technology nodes.

Responsibilities :

  • Participating in or leading next generation physical design, implementation, methodology and flow development.
  • Requirements :

  • BS / MS in EE / CS with 1 -3 years (3-5 years preferred) of hands-on experience in physical design and verification.
  • Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues using tools like;
  • ICC2, Innovus, Tempus, Primetime, Conformal

  • Good knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM / IR-Drop / crosstalk analysis
  • LI-MA1

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