At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The ideal candidate will have :
experience with SystemVerilog, VHDL, C / C++,SystemC or Specman
experience with UVM
ability to write scripts (Perl, Python or TCL)
strong software, HDL design and verification skills
ability to quickly analyze verification environments and design complexity
ability to interact effectively with both external customers and R&D teams
excellent communication, presentation, and interpersonal skills
BS, MS, or PhD in Electronic Engineering
3+ years of industry experience
We’re doing work that matters. Help us solve what others can’t.