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Principal Logic Design Engineer
As a member of the Logic Design Team for Xtensa processors you will be responsible for the micro-architecture development and specification of microprocessor cores, multiprocessor sub-systems and their peripherals.
You will design and implement the micro-architecture in Verilog or SystemVerilog RTL, simulate and debug its functions and run synthesis, place & route and other EDA scripts to meet timing, area and power goals.
You will also assist with developing testplans, writing functional diagnostics, debugging failures and analyzing coverage information.
You will work closely with the Design Verification and EDA teams.
The Position Requirements are :
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